// ==================================================================================
// RxPHY	: No input (1080@30p test pattern out)
// PCK		: 74.25MHz single data rate
// VD port	: BT1120 16bit VD_A(Y), VD_B(C)
// ==================================================================================
#define TP_VD_VD16_Size	5
const UINT TP_VD_VD16[2][TP_VD_VD16_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80008000},
	{ 0x000000c8, 0x04440004, 0x0fef0fef},
	{ 0x000000c8, 0x80000000, 0x80000000},
	
	{ 0x000000d2, 0x00000300, 0x00003f00},
	{ 0x000000de, 0x00002000, 0x0000f800}
},
{
	{ 0x000000c8, 0x00000000, 0x80008000},
	{ 0x000000c8, 0x00040444, 0x0fef0fef},
	{ 0x000000c8, 0x00008000, 0x00008000},
	
	{ 0x000000d2, 0x00000700, 0x00003f00},
	{ 0x000000de, 0x00008000, 0x0000f800}
}
};

// ==================================================================================
// RxPHY	: No input (1440@30p test pattern out)
// PCK		: 148.5MHz single data rate
// VD port	: BT1120 16bit VD_A(Y), VD_B(C)
// ==================================================================================
//#define TP_VD_VD16_Size	5
//const UINT TP_VD_VD16[2][TP_VD_VD16_Size][3] = {
//{	
//	{ 0x000000c8, 0x00000000, 0x80008000},
//	{ 0x000000c8, 0x03630003, 0x0fef0fef},
//	{ 0x000000c8, 0x80000000, 0x80000000},
//	
//	{ 0x000000d2, 0x00000300, 0x00003f00},
//	{ 0x000000de, 0x00002000, 0x0000f800}
//},
//{	
//	{ 0x000000c8, 0x00000000, 0x80008000},
//	{ 0x000000c8, 0x00030363, 0x0fef0fef},
//	{ 0x000000c8, 0x00008000, 0x00008000},
//	
//	{ 0x000000d2, 0x00000700, 0x00003f00},
//	{ 0x000000de, 0x00008000, 0x0000f800}
//}
//};

// ==================================================================================
// RxPHY	: No input (2160@30p test pattern out)
// PCK		: 297MHz single data rate
// VD port	: BT1120 16bit VD_A(Y), VD_B(C)
// ==================================================================================
//#define TP_VD_VD16_Size	5
//const UINT TP_VD_VD16[2][TP_VD_VD16_Size][3] = {
//{
//	{ 0x000000c8, 0x00000000, 0x80008000},
//	{ 0x000000c8, 0x02220002, 0x0fef0fef},
//	{ 0x000000c8, 0x80000000, 0x80000000},
//	
//	{ 0x000000d2, 0x00000300, 0x00003f00},
//	{ 0x000000de, 0x00002000, 0x0000f800}
//},
//{
//	{ 0x000000c8, 0x00000000, 0x00000000},	// dummy register
//	{ 0x000000c8, 0x00000000, 0x00000000},
//	{ 0x000000c8, 0x00000000, 0x00000000},
//	
//	{ 0x000000d2, 0x00000000, 0x00000000},
//	{ 0x000000de, 0x00000000, 0x00000000}
//}
//};

// ==================================================================================
// RxPHY	: HD-SDI (1.485Gbps)
// PCK		: 74.25MHz single data rate
// VD port	: BT1120 16bit VD_A(Y), VD_B(C)
// ==================================================================================
#define RX_HDSDI_VD16_Size	5
const UINT RX_HDSDI_VD16[2][RX_HDSDI_VD16_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80008000},
	{ 0x000000c8, 0x01010004, 0x0fef0fef},
	{ 0x000000c8, 0x80000000, 0x80000000},
	
	{ 0x000000d2, 0x00000300, 0x00003f00},
	{ 0x000000de, 0x00002000, 0x0000f800}
},
{
	{ 0x000000c8, 0x00000000, 0x80008000},
	{ 0x000000c8, 0x00010101, 0x0fef0fef},
	{ 0x000000c8, 0x00008000, 0x00008000},
	
	{ 0x000000d2, 0x00000700, 0x00003f00},
	{ 0x000000de, 0x00008000, 0x0000f800}
}
};

// ==================================================================================
// RxPHY	: EX-SDI 1.0 (270Mbps)
// PCK		: 74.25MHz single data rate
// VD port	: BT1120 16bit VD_A(Y), VD_B(C)
// ==================================================================================
#define RX_EX270_HD_VD16_Size	5
const UINT RX_EX270_HD_VD16[2][RX_EX270_HD_VD16_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80008000},
	{ 0x000000c8, 0x06660006, 0x0fef0fef},
	{ 0x000000c8, 0x80000000, 0x80000000},
	
	{ 0x000000d2, 0x00000300, 0x00003f00},
	{ 0x000000de, 0x00002000, 0x0000f800}
},
{
	{ 0x000000c8, 0x00000000, 0x80008000},
	{ 0x000000c8, 0x00060666, 0x0fef0fef},
	{ 0x000000c8, 0x00008000, 0x00008000},
	
	{ 0x000000d2, 0x00000700, 0x00003f00},
	{ 0x000000de, 0x00008000, 0x0000f800}
}
};

// ==================================================================================
// RxPHY	: EX-SDI 2.0 (135Mbps)
// PCK		: 74.25MHz single data rate
// VD port	: BT1120 16bit VD_A(Y), VD_B(C)
// ==================================================================================
#define RX_EX135_HD_VD16_Size	5
const UINT RX_EX135_HD_VD16[2][RX_EX135_HD_VD16_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80008000},
	{ 0x000000c8, 0x06660006, 0x0fef0fef},
	{ 0x000000c8, 0x80000000, 0x80000000},
	
	{ 0x000000d2, 0x00000300, 0x00003f00},
	{ 0x000000de, 0x00002000, 0x0000f800}
},
{
	{ 0x000000c8, 0x00000000, 0x80008000},
	{ 0x000000c8, 0x00060666, 0x0fef0fef},
	{ 0x000000c8, 0x00008000, 0x00008000},
	
	{ 0x000000d2, 0x00000700, 0x00003f00},
	{ 0x000000de, 0x00008000, 0x0000f800}
}
};

// ==================================================================================
// RxPHY	: EX-SDI 3G/4M (270Mbps)
// PCK		: 148.5MHz single data rate
// VD port	: BT1120 16bit VD_A(Y), VD_B(C)
// ==================================================================================
#define RX_EX270_3G_4M_VD16_Size	5
const UINT RX_EX270_3G_4M_VD16[2][RX_EX270_3G_4M_VD16_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80008000},
	{ 0x000000c8, 0x05050005, 0x0fef0fef},
	{ 0x000000c8, 0x80000000, 0x80000000},
	
	{ 0x000000d2, 0x00003300, 0x00003f00},
	{ 0x000000de, 0x00002000, 0x0000f800}
},
{
	{ 0x000000c8, 0x00000000, 0x80008000},
	{ 0x000000c8, 0x00050505, 0x0fef0fef},
	{ 0x000000c8, 0x00008000, 0x00008000},
	
	{ 0x000000d2, 0x00003700, 0x00003f00},
	{ 0x000000de, 0x00008000, 0x0000f800}
}
};

// ==================================================================================
// RxPHY	: 3G-SDI (2.97Gbps)
// PCK		: 148.5MHz single data rate
// VD port	: BT1120 16bit VD_A(Y), VD_B(C)
// ==================================================================================
#define RX_3GSDI_VD16_Size	5
const UINT RX_3GSDI_VD16[2][RX_3GSDI_VD16_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80008000},
	{ 0x000000c8, 0x00000000, 0x0fef0fef},
	{ 0x000000c8, 0x80000000, 0x80000000},
	
	{ 0x000000d2, 0x00003300, 0x00003f00},
	{ 0x000000de, 0x00002000, 0x0000f800}
},
{
	{ 0x000000c8, 0x00000000, 0x80008000},
	{ 0x000000c8, 0x00000000, 0x0fef0fef},
	{ 0x000000c8, 0x00008000, 0x00008000},
	
	{ 0x000000d2, 0x00003700, 0x00003f00},
	{ 0x000000de, 0x00008000, 0x0000f800}
}
};

// ==================================================================================
// RxPHY	: EX-SDI 4K (1.485Gbps)
// PCK		: 297MHz single data rate
// VD port	: BT1120 16bit VD_A(Y), VD_B(C)
// ==================================================================================
#define RX_EX1G5_4K_VD16_SDR_Size	5
const UINT RX_EX1G5_4K_VD16_SDR[2][RX_EX1G5_4K_VD16_SDR_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80008000},
	{ 0x000000c8, 0x02220002, 0x0fef0fef},
	{ 0x000000c8, 0x80000000, 0x80008000},	//	clock output 297Mhz to PCK_A/C Port
//	{ 0x000000c8, 0x80008000, 0x80008000},	//	clock output 297Mhz to PCK_B/D Port
	
	{ 0x000000d2, 0x00000300, 0x00003f30},
	{ 0x000000de, 0x00002000, 0x0000f800}	//	clock output 297Mhz to PCK_A/C Port
//	{ 0x000000de, 0x00008000, 0x0000f800}	//	clock output 297Mhz to PCK_B/D Port
},
{
	{ 0x000000c8, 0x00000000, 0x00000000},	// dummy register
	{ 0x000000c8, 0x00000000, 0x00000000},
	{ 0x000000c8, 0x00000000, 0x00000000},

	{ 0x000000d2, 0x00000000, 0x00000000},
	{ 0x000000de, 0x00000000, 0x00000000}
}
};

// ==================================================================================
// RxPHY	: No input (1080@30p test pattern out)
// PCK		: 148.5MHz single data rate
// VD port	: Multiplexed BT1120 8bit VD_A(YC), VD_B(YC)
// ==================================================================================
#define TP_VD_VD8_Size	5
const UINT TP_VD_VD8[2][TP_VD_VD8_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80000000},
	{ 0x000000c8, 0x04430000, 0x0fef0000},
	{ 0x000000c8, 0x80000000, 0x80000000},
	
	{ 0x000000d2, 0x00003000, 0x00003f00},
	{ 0x000000de, 0x00000000, 0x0000c000}
},
{
	{ 0x000000c8, 0x00000000, 0x00008000},
	{ 0x000000c8, 0x00000443, 0x00000fef},
	{ 0x000000c8, 0x00008000, 0x00008000},
	
	{ 0x000000d2, 0x00000020, 0x00000f30},
	{ 0x000000de, 0x00000000, 0x00003800}
}
};

// ==================================================================================
// RxPHY	: No input (1440@30p test pattern out)
// PCK		: 148.5MHz double data rate
// VD port	: Multiplexed BT1120 8bit VD_A(YC), VD_B(YC)
// ==================================================================================
//#define TP_VD_VD8_Size	5
//const UINT TP_VD_VD8[2][TP_VD_VD8_Size][3] = {
//{	
//	{ 0x000000c8, 0x00000000, 0x80000000},
//	{ 0x000000c8, 0x03630000, 0x0fef0000},
//	{ 0x000000c8, 0x80000000, 0x80000000},
//	
//	{ 0x000000d2, 0x00000000, 0x00003f00},
//	{ 0x000000de, 0x00000000, 0x0000c000}
//},
//{	
//	{ 0x000000c8, 0x00000000, 0x00008000},
//	{ 0x000000c8, 0x00000363, 0x00000fef},
//	{ 0x000000c8, 0x00008000, 0x00008000},
//	
//	{ 0x000000d2, 0x00000000, 0x00000f30},
//	{ 0x000000de, 0x00000000, 0x00003800}
//}
//};

// ==================================================================================
// RxPHY	: No input (2160@30p test pattern out)
// PCK		: 148.5MHz double data rate
// VD port	: BT1120 16bit VD_A(Y), VD_B(C)
// ==================================================================================
//#define TP_VD_VD8_Size	5
//const UINT TP_VD_VD8[2][TP_VD_VD8_Size][3] = {
//{
//	{ 0x000000c8, 0x00000000, 0x80000000},
//	{ 0x000000c8, 0x03230000, 0x7fef0000},
//	{ 0x000000c8, 0x80000000, 0x80000000},
//	
//	{ 0x000000d2, 0x00000b00, 0x00003f00},
//	{ 0x000000de, 0x00002000, 0x0000f800}
//},
//{
//	{ 0x000000c8, 0x00000000, 0x00000000},	// dummy register
//	{ 0x000000c8, 0x00000000, 0x00000000},
//	{ 0x000000c8, 0x00000000, 0x00000000},
//	
//	{ 0x000000d2, 0x00000000, 0x00000000},
//	{ 0x000000de, 0x00000000, 0x00000000}
//}
//};

// ==================================================================================
// RxPHY	: HD-SDI (1.485Gbps)
// PCK		: 148.5MHz single data rate
// VD port	: Multiplexed BT1120 8bit VD_A(YC), VD_B(YC)
// ==================================================================================
#define RX_HDSDI_VD8_Size	5
const UINT RX_HDSDI_VD8[2][RX_HDSDI_VD8_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80000000},
	{ 0x000000c8, 0x01000000, 0x0fef0000},
	{ 0x000000c8, 0x80000000, 0x80000000},
	
	{ 0x000000d2, 0x00003000, 0x00003f00},
	{ 0x000000de, 0x00000000, 0x0000c000}
},
{
	{ 0x000000c8, 0x00000000, 0x00008000},
	{ 0x000000c8, 0x00000100, 0x00000fef},
	{ 0x000000c8, 0x00008000, 0x00008000},
	
	{ 0x000000d2, 0x00000030, 0x00000f30},
	{ 0x000000de, 0x00000000, 0x00003800}
}
};
#if 1
// ==================================================================================
// RxPHY	: EX-SDI 1.0 (270Mbps)
// PCK		: 148.5MHz single data rate
// VD port	: BT656 8bit VD_A(YC), VD_B(YC)
// ==================================================================================
#define RX_EX270_HD_VD8_Size	6
const UINT RX_EX270_HD_VD8[2][RX_EX270_HD_VD8_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80000000},
	{ 0x000000c8, 0x06650000, 0x0fef0000},
	{ 0x000000c8, 0x80000000, 0x80000000},
	
	{ 0x000000d2, 0x00003000, 0x00003f00},
	{ 0x000000de, 0x00000000, 0x0000c000},
	{ 0x00000061, 0x00400000, 0x00400000} // BT656 Enable #A-CH
},
{
	{ 0x000000c8, 0x00000000, 0x00008000},
	{ 0x000000c8, 0x00000665, 0x00000fef},
	{ 0x000000c8, 0x00008000, 0x00008000},
	
	{ 0x000000d2, 0x00000030, 0x00000f30},
	{ 0x000000de, 0x00000000, 0x00003800},
	{ 0x00000062, 0x00400000, 0x00400000} // BT656 Enable #B-CH
}
};

// ==================================================================================
// RxPHY	: EX-SDI 2.0 (135Mbps)
// PCK		: 148.5MHz single data rate
// VD port	: BT656 8bit VD_A(YC), VD_B(YC)
// ==================================================================================
#define RX_EX135_HD_VD8_Size	6
const UINT RX_EX135_HD_VD8[2][RX_EX135_HD_VD8_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80000000},
	{ 0x000000c8, 0x06650000, 0x0fef0000},
	{ 0x000000c8, 0x80000000, 0x80000000},
	
	{ 0x000000d2, 0x00003000, 0x00003f00},
	{ 0x000000de, 0x00000000, 0x0000c000},
	{ 0x00000061, 0x00400000, 0x00400000} // BT656 Enable #A-CH
},
{
	{ 0x000000c8, 0x00000000, 0x00008000},
	{ 0x000000c8, 0x00000665, 0x00000fef},
	{ 0x000000c8, 0x00008000, 0x00008000},
	
	{ 0x000000d2, 0x00000030, 0x00000f30},
	{ 0x000000de, 0x00000000, 0x00003800},
	{ 0x00000062, 0x00400000, 0x00400000} // BT656 Enable #B-CH
}
};
#else // mUT

// ==================================================================================
// RxPHY	: EX-SDI 1.0 (270Mbps)
// PCK		: 148.5MHz single data rate
// VD port	: Multiplexed BT1120 8bit VD_A(YC), VD_B(YC)
// ==================================================================================
#define RX_EX270_HD_VD8_Size	5
const UINT RX_EX270_HD_VD8[2][RX_EX270_HD_VD8_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80000000},
	{ 0x000000c8, 0x06650000, 0x0fef0000},
	{ 0x000000c8, 0x80000000, 0x80000000},
	
	{ 0x000000d2, 0x00003000, 0x00003f00},
	{ 0x000000de, 0x00000000, 0x0000c000}
},
{
	{ 0x000000c8, 0x00000000, 0x00008000},
	{ 0x000000c8, 0x00000665, 0x00000fef},
	{ 0x000000c8, 0x00008000, 0x00008000},
	
	{ 0x000000d2, 0x00000030, 0x00000f30},
	{ 0x000000de, 0x00000000, 0x00003800}
}
};

// ==================================================================================
// RxPHY	: EX-SDI 2.0 (135Mbps)
// PCK		: 148.5MHz single data rate
// VD port	: Multiplexed BT1120 8bit VD_A(YC), VD_B(YC)
// ==================================================================================
#define RX_EX135_HD_VD8_Size	5
const UINT RX_EX135_HD_VD8[2][RX_EX135_HD_VD8_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80000000},
	{ 0x000000c8, 0x06650000, 0x0fef0000},
	{ 0x000000c8, 0x80000000, 0x80000000},
	
	{ 0x000000d2, 0x00003000, 0x00003f00},
	{ 0x000000de, 0x00000000, 0x0000c000}
},
{
	{ 0x000000c8, 0x00000000, 0x00008000},
	{ 0x000000c8, 0x00000665, 0x00000fef},
	{ 0x000000c8, 0x00008000, 0x00008000},
	
	{ 0x000000d2, 0x00000030, 0x00000f30},
	{ 0x000000de, 0x00000000, 0x00003800}
}
};
#endif
// ==================================================================================
// RxPHY	: EX-SDI 3G/4M (270Mbps)
// PCK		: 148.5MHz double data rate
// VD port	: Multiplexed BT1120 8bit VD_A(YC), VD_B(YC)
// ==================================================================================
#define RX_EX270_3G_4M_VD8_Size	5
const UINT RX_EX270_3G_4M_VD8[2][RX_EX270_3G_4M_VD8_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80000000},
	{ 0x000000c8, 0x05050000, 0x0fef0000},
	{ 0x000000c8, 0x80000000, 0x80000000},
	
	{ 0x000000d2, 0x00000000, 0x00003f00},
	{ 0x000000de, 0x00000000, 0x0000c000}
},
{
	{ 0x000000c8, 0x00000000, 0x00008000},
	{ 0x000000c8, 0x00000505, 0x00000fef},
	{ 0x000000c8, 0x00008000, 0x00008000},
	
	{ 0x000000d2, 0x00000000, 0x00000f30},
	{ 0x000000de, 0x00000000, 0x00003800}
}
};

// ==================================================================================
// RxPHY	: 3G-SDI (2.97Gbps)
// PCK		: 148.5MHz double data rate
// VD port	: Multilexed BT1120 8bit VD_A(YC), VD_B(YC)
// ==================================================================================
#define RX_3GSDI_VD8_Size	5
const UINT RX_3GSDI_VD8[2][RX_3GSDI_VD8_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80000000},
	{ 0x000000c8, 0x00000000, 0x0fef0000},
	{ 0x000000c8, 0x80000000, 0x80000000},
	
	{ 0x000000d2, 0x00000000, 0x00003f00},
	{ 0x000000de, 0x00000000, 0x0000c000}
},
{
	{ 0x000000c8, 0x00000000, 0x00008000},
	{ 0x000000c8, 0x00000000, 0x00000fef},
	{ 0x000000c8, 0x00008000, 0x00008000},
	
	{ 0x000000d2, 0x00000000, 0x00000f30},
	{ 0x000000de, 0x00000000, 0x00003800}
}
};

// ==================================================================================
// RxPHY	: EX-SDI 4K (1.485Gbps)
// PCK		: 148.5MHz double data rate
// VD port	: BT1120 16bit VD_A(Y), VD_B(C)
// ==================================================================================
#define RX_EX1G5_4K_VD16_DDR_Size	5
const UINT RX_EX1G5_4K_VD16_DDR[2][RX_EX1G5_4K_VD16_DDR_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80008000},
	{ 0x000000c8, 0x03230003, 0x0fef0fef},
	{ 0x000000c8, 0x80000000, 0x80008000},	//	clock output 148.5Mhz to PCK_A/C Port
//	{ 0x000000c8, 0x80008000, 0x80008000},	//	clock output 148.5Mhz to PCK_B/D Port
	
	{ 0x000000d2, 0x00000b00, 0x00003f30},
	{ 0x000000de, 0x00002000, 0x0000f800}	//	clock output 148.5Mhz to PCK_A/C Port
//	{ 0x000000de, 0x00008000, 0x0000f800}	//	clock output 148.5Mhz to PCK_B/D Port
},
{
	{ 0x000000c8, 0x00000000, 0x00000000},	// dummy register
	{ 0x000000c8, 0x00000000, 0x00000000},
	{ 0x000000c8, 0x00000000, 0x00000000},

	{ 0x000000d2, 0x00000000, 0x00000000},
	{ 0x000000de, 0x00000000, 0x00000000}
}
};

// ==================================================================================
// RxPHY	: HD-SDI (1.485Gbps)
// PCK		: 148.5MHz double data rate
// VD port	: 2Ch-Multilexed BT656 8bit VD_A(YC)
// ==================================================================================
#define RX_HDSDI_VDTDM_Size	9
const UINT RX_HDSDI_VDTDM[2][RX_HDSDI_VDTDM_Size][3] = {
{	
	{ 0x000000c8, 0x00000000, 0x80000000},	// VD_A Disable
	{ 0x000000c8, 0x00000000, 0x0fef0000},	// PCK_A, Internal clock selection
	{ 0x000000c8, 0x80000000, 0x80000000},	// VD_A Enable
	
	{ 0x000000c6, 0x00000000, 0x01000000},	// MUX Disable
	{ 0x000000c6, 0x00100000, 0x00730000},	// MUX_PCK_A, MUX_DPCK_A select 
	{ 0x000000c6, 0x01000000, 0x01000000},	// MUX Enable 
	
	{ 0x000000d1, 0x00000000, 0x0000c0cc},	// Internal data MUX selection
	{ 0x000000d2, 0x00002000, 0x00003000},	// Internal data MUX selection
	
	{ 0x000000de, 0x00000000, 0x0000c000}
},
{	
	{ 0x000000c8, 0x00000000, 0x00008000},	// PCK_B enable
	{ 0x000000c8, 0x00000000, 0x00000fef},	// PCK_B, Internal clock selection
	{ 0x000000c8, 0x00000000, 0x00008000},	// PCK_B enable
	
	{ 0x000000c6, 0x00000000, 0x01000000},	// MUX Disable
	{ 0x000000c6, 0x00001000, 0x00007300},	// MUX_PCK_B, MUX_DPCK_B select 
	{ 0x000000c6, 0x01000000, 0x01000000},	// MUX Enable 
	
	{ 0x000000d1, 0x00000000, 0x00003033},	// VDO_DI_B, MUX_DI_B Select
	{ 0x000000d2, 0x00000000, 0x00000030},	// Internal data MUX selection
	
	{ 0x000000de, 0x00003800, 0x00003800}
}
};

// ==================================================================================
// RxPHY	: EX-SDI 1.0 (270Mbps)
// PCK		: 148.5MHz double data rate
// VD port	: 2Ch-Multilexed BT656 8bit VD_A(YC)
// ==================================================================================
#define RX_EX270_HD_VDTDM_Size	9
const UINT RX_EX270_HD_VDTDM[2][RX_EX270_HD_VDTDM_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80000000},	// VD_A Disable
	{ 0x000000c8, 0x00050000, 0x0fef0000},	// PCK_A, Internal clock selection
	{ 0x000000c8, 0x80000000, 0x80000000},	// VD_A Enable
	
	{ 0x000000c6, 0x00000000, 0x01000000},	// MUX Disable
	{ 0x000000c6, 0x00520000, 0x00730000},	// MUX_PCK_A, MUX_DPCK_A select 
	{ 0x000000c6, 0x01000000, 0x01000000},	// MUX Enable 
	
	{ 0x000000d1, 0x00000080, 0x0000c0cc},	// Internal data MUX selection
	{ 0x000000d2, 0x00002000, 0x00003000},	// Internal data MUX selection
	
	{ 0x000000de, 0x00000000, 0x0000c000}
},
{
	{ 0x000000c8, 0x00000000, 0x00008000},	// PCK_B enable
	{ 0x000000c8, 0x00000000, 0x00000fef},	// PCK_B, Internal clock selection
	{ 0x000000c8, 0x00000000, 0x00008000},	// PCK_B enable
	
	{ 0x000000c6, 0x00000000, 0x01000000},	// MUX Disable
	{ 0x000000c6, 0x00005200, 0x00007300},	// MUX_PCK_B, MUX_DPCK_B select 
	{ 0x000000c6, 0x01000000, 0x01000000},	// MUX Enable 
	
	{ 0x000000d1, 0x00000020, 0x00003033},	// VDO_DI_B, MUX_DI_B Select
	{ 0x000000d2, 0x00000000, 0x00000030},	// Internal data MUX selection
	
	{ 0x000000de, 0x00003800, 0x00003800}
}
};

// ==================================================================================
// RxPHY	: EX-SDI 2.0 (135Mbps)
// PCK		: 148.5MHz double data rate
// VD port	: 2Ch-Multilexed BT656 8bit VD_A(YC)
// ==================================================================================
#define RX_EX135_HD_VDTDM_Size	9
const UINT RX_EX135_HD_VDTDM[2][RX_EX135_HD_VDTDM_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80000000},	// VD_A Disable
	{ 0x000000c8, 0x00050000, 0x0fef0000},	// PCK_A, Internal clock selection
	{ 0x000000c8, 0x80000000, 0x80000000},	// VD_A Enable
	
	{ 0x000000c6, 0x00000000, 0x01000000},	// MUX Disable
	{ 0x000000c6, 0x00520000, 0x00730000},	// MUX_PCK_A, MUX_DPCK_A select 
	{ 0x000000c6, 0x01000000, 0x01000000},	// MUX Enable 
	
	{ 0x000000d1, 0x00000080, 0x0000c0cc},	// Internal data MUX selection
	{ 0x000000d2, 0x00002000, 0x00003000},	// Internal data MUX selection
	
	{ 0x000000de, 0x00000000, 0x0000c000}
},
{
	{ 0x000000c8, 0x00000000, 0x00008000},	// PCK_B enable
	{ 0x000000c8, 0x00000000, 0x00000fef},	// PCK_B, Internal clock selection
	{ 0x000000c8, 0x00000000, 0x00008000},	// PCK_B enable
	
	{ 0x000000c6, 0x00000000, 0x01000000},	// MUX Disable
	{ 0x000000c6, 0x00005200, 0x00007300},	// MUX_PCK_B, MUX_DPCK_B select 
	{ 0x000000c6, 0x01000000, 0x01000000},	// MUX Enable 
	
	{ 0x000000d1, 0x00000020, 0x00003033},	// VDO_DI_B, MUX_DI_B Select
	{ 0x000000d2, 0x00000000, 0x00000030},	// Internal data MUX selection
	
	{ 0x000000de, 0x00003800, 0x00003800}
}
};

// ==================================================================================
// RxPHY	: EX-SDI TDM (1.485Gbps, RxPHY)
// PCK		: 148.5MHz double data rate
// VD port	: 2Ch-Multilexed BT656 8bit VD_A(YC)
// ==================================================================================
#define RX_EXTDM_RX_VDTDM_Size	9
const UINT RX_EXTDM_RX_VDTDM[2][RX_EXTDM_RX_VDTDM_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80000000},	// VD_A Disable
	{ 0x000000c8, 0x00030000, 0x0fef0000},	// PCK_A, Internal clock selection
	{ 0x000000c8, 0x80000000, 0x80000000},	// VD_A Enable
	
	{ 0x000000c6, 0x00000000, 0x01000000},	// MUX Disable
	{ 0x000000c6, 0x00310000, 0x00730000},	// MUX_PCK_A, MUX_DPCK_A select 
	{ 0x000000c6, 0x01000000, 0x01000000},	// MUX Enable 
	
	{ 0x000000d1, 0x00000080, 0x0000c0cc},	// Internal data MUX selection
	{ 0x000000d2, 0x00002000, 0x00003000},	// Internal data MUX selection
	
	{ 0x000000de, 0x00000000, 0x0000c000}
},
{
	{ 0x000000c8, 0x00000000, 0x00008000},	// PCK_B enable
	{ 0x000000c8, 0x00000000, 0x00000fef},	// PCK_B, Internal clock selection
	{ 0x000000c8, 0x00000000, 0x00008000},	// PCK_B enable
	
	{ 0x000000c6, 0x00000000, 0x01000000},	// MUX Disable
	{ 0x000000c6, 0x00003100, 0x00007300},	// MUX_PCK_B, MUX_DPCK_B select 
	{ 0x000000c6, 0x01000000, 0x01000000},	// MUX Enable 
	
	{ 0x000000d1, 0x00000020, 0x00003033},	// VDO_DI_B, MUX_DI_B Select
	{ 0x000000d2, 0x00000000, 0x00000030},	// Internal data MUX selection
	
	{ 0x000000de, 0x00003800, 0x00003800}
}
};

// ==================================================================================
// RxPHY	: EX-SDI TDM (1.485Gbps, ICI)
// PCK		: 148.5MHz double data rate
// VD port	: 2Ch-Multilexed BT656 8bit VD_A(YC)
// ==================================================================================
#define RX_EXTDM_IC_VDTDM_Size	9
const UINT RX_EXTDM_IC_VDTDM[2][RX_EXTDM_IC_VDTDM_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80000000},	// VD_A Disable
	{ 0x000000c8, 0x00070000, 0x0fef0000},	// PCK_A, Internal clock selection
	{ 0x000000c8, 0x80000000, 0x80000000},	// VD_A Enable
	
	{ 0x000000c6, 0x00000000, 0x01000000},	// MUX Disable
	{ 0x000000c6, 0x00730000, 0x00730000},	// MUX_PCK_A, MUX_DPCK_A select 
	{ 0x000000c6, 0x01000000, 0x01000000},	// MUX Enable 
	
	{ 0x000000d1, 0x00000080, 0x0000c0cc},	// Internal data MUX selection
	{ 0x000000d2, 0x00002000, 0x00003000},	// Internal data MUX selection
	
	{ 0x000000de, 0x00000000, 0x0000c000}
},
{
	{ 0x000000c8, 0x00000000, 0x00008000},	// PCK_B enable
	{ 0x000000c8, 0x00000000, 0x00000fef},	// PCK_B, Internal clock selection
	{ 0x000000c8, 0x00000000, 0x00008000},	// PCK_B enable
	
	{ 0x000000c6, 0x00000000, 0x01000000},	// MUX Disable
	{ 0x000000c6, 0x00007300, 0x00007300},	// MUX_PCK_B, MUX_DPCK_B select 
	{ 0x000000c6, 0x01000000, 0x01000000},	// MUX Enable 
	
	{ 0x000000d1, 0x00000020, 0x00003033},	// VDO_DI_B, MUX_DI_B Select
	{ 0x000000d2, 0x00000000, 0x00000030},	// Internal data MUX selection
	
	{ 0x000000de, 0x00003800, 0x00003800}
}
};

// ==================================================================================
// RxPHY	: No input (1080@30p test pattern out)
// PCK		: 148.5MHz double data rate
// VD port	: 2Ch-Multilexed BT656 8bit VD_A(YC)
// ==================================================================================
#define TP_VD_VDTDM_Size	9
const UINT TP_VD_VDTDM[2][TP_VD_VDTDM_Size][3] = {
{
	{ 0x000000c8, 0x00000000, 0x80000000},	// VD_A Disable
	{ 0x000000c8, 0x00030000, 0x0fef0000},	// PCK_A, Internal clock selection
	{ 0x000000c8, 0x80000000, 0x80000000},	// VD_A Enable
	
	{ 0x000000c6, 0x00000000, 0x01000000},	// MUX Disable
	{ 0x000000c6, 0x00310000, 0x00730000},	// MUX_PCK_A, MUX_DPCK_A select 
	{ 0x000000c6, 0x01000000, 0x01000000},	// MUX Enable 
	
	{ 0x000000d1, 0x00000000, 0x000000cc},	// Internal data MUX selection
	{ 0x000000d2, 0x00002000, 0x00003000},	// Internal data MUX selection
	
	{ 0x000000de, 0x00000000, 0x0000c000}
},
{
	{ 0x000000c8, 0x00000000, 0x00008000},	// PCK_B enable
	{ 0x000000c8, 0x00000000, 0x00000fef},	// PCK_B, Internal clock selection
	{ 0x000000c8, 0x00000000, 0x00008000},	// PCK_B enable
	
	{ 0x000000c6, 0x00000000, 0x01000000},	// MUX Disable
	{ 0x000000c6, 0x00003100, 0x00007300},	// MUX_PCK_B, MUX_DPCK_B select 
	{ 0x000000c6, 0x01000000, 0x01000000},	// MUX Enable 
	
	{ 0x000000d1, 0x00000000, 0x00000033},	// VDO_DI_B, MUX_DI_B Select
	{ 0x000000d2, 0x00000000, 0x00000030},	// Internal data MUX selection
	
	{ 0x000000de, 0x00003800, 0x00003800}
}
};


// =================================================================================
// RxPHY	: -
// PCK		: Hi-z
// VD port	: Hi-z
// ==================================================================================
#define HIZ_VD_Size	1
const UINT HIZ_VD[2][HIZ_VD_Size][3] = {
{	
	{ 0x000000de, 0x0000c000, 0x0000c000}
},
{	
	{ 0x000000de, 0x00003800, 0x00003800}
}
};
